Digital Verification

Virtual Platform Development

Long before an ASIC is available, the experienced Eximius team can help you to build simulation models that run several orders of magnitude faster than RTL simulations. These models can be used for architectural exploration, performance evaluation and to accelerate firmware development.

The Eximius engineering team also has significant experience in building models for the mobile applications which help you to reduce the design cycles significantly by providing you virtual platform development services that help to get your products to the market much faster.

Our team is exceptionally strong in the following areas:

  • Designing Systems On a Chip (SOC) using single or multiple cores from ARM
  • Designing high performance ASICs that require the right partitioning of functionality between fixed function units (“digital logic”) and data plane CPU cores.
  • Integrating high speed serial interfaces (SERDES) on-chip.
  • Integrating mixed signal IP such as Video DACs, ADC’s, and a variety of different sensors.
  • Designing for low power using techniques such as Clock Gating, Power Islands or Power Gating.
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Functional (RTL) Design

Our expertise in functional RTL design are:

  • Design Systems On a Chip (SOC) using single or multiple cores from ARM
  • Design high performance ASICs that require the right partitioning of functionality between fixed function units (“digital logic”) and data plane CPU cores
  • Design for low power using techniques such as Clock Gating, Power Islands or Power Gating
  • Integrate high speed serial interfaces (SERDES) on-chip
  • Integrate mixed signal IP such as Video DACs, ADC’s, and a variety of different sensors

Block Level and Full chip RTL and Verification

Over the last decade, newer languages such as SystemVerilog have allowed verification engineers to significantly improve their productivity in building and maintaining complex verification environments. The availability of a large body of pre-verified components provided by standardized methodologies such as eRM, VMM, OVM and UVM have also helped significantly.

At Eximius we have experience in building large maintainable verification environments in both SystemC and SystemVerilog. We can help to preserve your investment in legacy simulation environments or help you to build a new one from starting to inception.

Ineffective utilization of newer verification techniques in various verification organizations have led to the following problems:

  • Increased use of license, compute and storage resources due to sub-optimal constraining of testbench stimulus.
  • Lack of predictability in verification schedules

Our verification team has been successful at avoiding these problems by not relying purely on a single verification methodology. Based on the complexity of the design-under-test (DUT), we engage one or more of the following methods.

  • Directed Test Cases
  • Constrained Random Verification using golden reference models
  • Assertion based verification
  • Formal verification to validate “ASIC-style” DUT against a golden reference model

We also use code and functional coverage metrics throughout our verification cycle to conserve simulation resources and assure predictability of the schedule.

DFT

Our DFT team works very closely with the RTL design team to ensure proper compatibility with the design architecture. In addition, the DFT team works with the physical implementation team to ensure that during the implementation phase all clocking, timing, connectivity and congestion are accounted for. Overall this ensures effortless implementation while maintaining excellent test coverage.

Eximius offers a complete suite of DFT services as below but not limited to the following:

  • Scan Insertion
  • Logic BIST
  • Memory BIST
  • Boundary Scan Insertion
  • ATPG Compression
  • Fault Simulation

"Just because something doesn’t do what you planned it to do doesn’t mean it’s useless."

Thomas Edison