Requisition : EXH-007
Experience : 2 to 7
Location : Bangalore
Job Overview :
- Complete understanding of DFT concepts and lower geometry SOC designs.
- Experienced in various aspects of DFT -Scan insertion, ATPG, MBIST & JTAG.
- Responsible for Designing and Implementing DFT techniques. (Boundary Scan, Memory BIST, Scan Insertion, ATPG) on complex SOCs to improve testability
- post-silicon debug is an added advantage.
- Experience with industry Standard tools is highly desirable.
- Good exposure to STA tool. Assist STA team in timing closure for DFT modes.
- Strong problem solving & debugging skills are a must.
- Expertise in scripting languages such as Perl, TCL, shell