Requisition : EXUS/114
Location : San Jose, CA
Include all aspects of physical design including but not limited to Synthesis, Floorplanning, Place and Route, Clock Tree Synthesis, Clock Distribution, IP integration, Extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and final Tape Out. Block/full chip level floor planning, placement techniques, power grid design and clock tree design. Perform STA and multi-mode, multi-scenario environments. Tool flow experience either using ICC/ICC2, SOC Encounter, PrimeTime and Calibre. Perform low power flow (power gating, multi-Vt, voltage islands, dynamic voltage scaling, body biasing, etc.). To Perform physical implementation of SoC designs. Design hierarchy diagram. Provide data flow of the design. Top level clocking/reset diagram. Ensure top level logic is minimal. Lint is performed, and warnings/errors are understood and prioritized. Quality of the incoming netlist. Timing constraints are error free. Develop physical design methodologies and scripts. Track timing, area, and QoR on a regular basis. Provide feedback to RTL team for fixes. Area, timing, and congestion improvements.
Required Masters or foreign equivalent in CS, Electronics, VLSI Design, VLSI-CAD, CIS, Engineering (Any), MIS or any related field. Requires +1 year of experience in the job offered, Verification Engineer, Electronics Engineer, Physical Design Engineer, Design Engineer, or related. Must be able to travel/relocate to various client sites throughout the U.S.
Eximius Design and its related business units provide Equal Employment Opportunity (EEO) to all qualified applicants without regard to race, color, religion, sex, or national origin.