Senior DFT engineer

Requisition : EXUS/109

Experience : 8-10 year

Location : USA

Eximius Design is seeking an outstanding DFT (Design For Test)engineer in San Jose, CA.

This position offers the opportunity to work on a state-of-the-art technology and have a real impact in a dynamic, technology-focused company impacting product lines ranging from Augmented Reality, IOT, Virtual Reality, Cloud Infrastructure and Networking.

Responsibilities and Duties

  • Responsible for all industry standard Design For Test (DFT) solutions for complex and low power chips using leading edge technologies.
  • Develop DFT logic insertion in RTL/gate.
  • Perform ATPG and test coverage debug, zero delay and SDF simulations for ATPG patterns
  • Good experience on Mentor Tessent MBIST flow, Synopsys DFTMAX OCC, scan compression flow, TetraMAX ATPG, VCS, Verdi, LEC
  • Support end operations team on silicon bring-up and yield improvement including pattern generation and debug, failure analysis, ATPG diagnostic flow automation.
  • Work closely with front-end and back-end teams for STA, physical design and logic issues

Qualifications and Skills

  • Must have a deep understanding of DFT related tasks. Including but not limited to scan insertion, memory BIST, Logic BIST, Serdes and IO test, JTAG, and boundary scan logic features on the chips
  • Should have 8-10 years plus of experience.
  • Deep knowledge of ATE and Functional tests required
  • Strong knowledge of logic design techniques
  • RTL/Logic design experience is a plus
  • Verification experience is a plus
  • Timing closure and timing constraints understanding for DFT modes is required
  • Strong communication and interpersonal skills
  • Experience with Perl or other scripting languages is required

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Eximius Design and its related business units provide Equal Employment Opportunity (EEO) to all qualified applicants without regard to race, color, religion, sex, or national origin.