Senior DFT Engineer/Member of Technical Staff

Requisition : EXUS/101

Experience : 8+ years

Location : USA

Job Overview :

  • Responsible for all industry standard Design For Test (DFT) solutions for complex and low power chips using leading edge technologies.
  • Develop DFT specifications and drive DFT architecture and for designs.
  • Perform ATPG pattern generation along with custom patterns for IP.
  • Implement memory BIST architecture, verification and memory test patterns.
  • Document the test-benches to make them more usable by other members of the team.
  • Support end operations team on silicon bring-up and yield improvement including pattern generation and debug, failure analysis, ATPG diagnostic flow automation.
  • Work closely with front-end and back-end teams for STA, physical design and logic issues

Qualification :

  • 8+ years of experience in DFT related tasks
  • Must have a deep understanding of DFT related tasks. Including but not limited to scan insertion, memory BIST, Logic BIST, Serdes and IO test, JTAG, and boundary scan logic features on the chips
  • Deep knowledge of ATE and Functional tests required
  • Knowledge of SRAM, CAM and register file internal circuitry and organization
  • Strong knowledge of logic design techniques
  • RTL/Logic design experience is a plus
  • Verification experience is a plus
  • Timing closure and timing constraints understanding for DFT modes is required
  • Strong communication and interpersonal skills
  • Experience with Perl or other scripting languages is required