Senior Physical Design Engineer/Member of Technical Staff

Requisition : EXUS/103

Experience : 8+ years

Location : USA

Job Overview :

  • Perform physical implementation of SoC designs
  • Responsible for steps including synthesis, floorplanning, place and route, power/clock distribution, congestion analysis, timing closure and final physical verification
  • Perform technical evaluations of vendors, process nodes and IP, and provide recommendations accordingly.
  • Develop physical design methodologies and scripts
  • Opportunity to mentor new team members

Qualification :

  • Must possess 8+ years of hands on experience in physical design
  • Experience in block/full chip level floorplanning, placement techniques, power grid design and clock tree design
  • Expertise in low power flow (power gating, multi-Vt, voltage islands, dynamic voltage scaling, body biasing, etc) is a plus
  • Deep understanding of physical effects in DSM technologies (28nm,16nm and below)
  • Well versed with the complete RTL to GDS design flow for hierarchical designs.
  • Deep experience in STA and multi-mode, multi-scenario environments
  • Experience in synthesis flow with involvement in multiple tape outs is a plus
  • Expertise in DRC-LVS closure with ICV or Calibre (16nm experience would be plus ) .
  • Good understanding of Reliability verification checks EM, IR etc.
  • EDA Tool Experience:
    • DC/DCT, RC/Genus, ICC/ICC2, Encounter/Innovus, PrimeTime-SI, StarXT, ICV, Conformal LEC, Redhawk
  • Proficiency in scripting languages such as, Perl, Tcl and make is required.
  • Self-starter, motivated and highly efficient
  • Strong communication and interpersonal skills
  • Masters degree in Electrical/Computer Engineering is preferred