Requisition : EXH-004

Experience : 2 to 10

Location : BLR/Hyd

Job Overview :

  •  Full chip and block level timing closure throughout entire design process (RTL, Synthesis, Place and Route and STA Signoff)
  • Develop, enhance and maintain all STA flows and methodology for multiple designs and across different technologies
  •  Generate STA constraints for both full chip and block level