Requisition : EXH-005

Experience : 2 to 10

Location : BLR/Hyd

Job Overview :

  • Expertise in Synopsys Design Compiler Synthesis – DCT/DCG and/or Cadence RC/Genus
  • Hands on in multi-voltage, power aware synthesis, UPF flows in synthesis
  • Expertise in formal verification with Cadence LEC/ Synopsys VC formal
  • Expertise in writing and debugging timing constraints
  • Expertise in full chip STA, hands on in Primetime is a strong plus
  • Good understanding of RTL to GDS flow.
  • Expertise in Perl and/or TCL scripting is a must
  • Knowledge in Verilog and VHDL is a must